1. Field of the Invention
This document is related to a plasma display panel, in particular to a plasma display apparatus capable of preventing an error discharge or an error writing of a discharge cell.
2. Description of the Background Art
In a conventional plasma display panel, one unit cell is provided at a space between barrier ribs formed between a front panel and a rear panel. A main discharge gas such as neon (Ne), helium (He) or a mixture (He+Ne) of neon and helium and an inert gas containing a small amount of xenon (Xe) fill each cell. When a discharge occurs using a high frequency voltage, the inert gas generates vacuum ultraviolet rays and phosphors provided between the barrier ribs are stimulated to emit light, thereby realizing an image. The plasma display panel is considered as one of the next generation display devices due to its thin profile and light weigh construction.
FIG. 1 illustrates a structure of a conventional plasma display panel.
As shown in FIG. 1, a plasma display panel includes a front panel 100 and a rear panel 110. The front panel 100 has a plurality of sustain electrode pairs arranged with a scan electrode 102 and a sustain electrode 103 each paired and formed on a front glass 101, which is a display surface for displaying the image thereon. The rear panel 110 has a plurality of address electrodes 113 arranged to intersect with the plurality of sustain electrode pairs on a rear glass 111, which is spaced apart in parallel with and sealed to the front panel 100.
The front panel 100 includes the paired scan electrode 102 and the paired sustain electrode 103 for performing a mutual discharge in one pixel and sustaining an emission of light. Each of the paired scan electrode 102 and the paired sustain electrode 103 has a transparent electrode (a) formed of indium-tin-oxide (ITO) and a bus electrode (b) formed of metal. The scan electrode 102 and the sustain electrode 103 are covered with at least one dielectric layer 104, which controls a discharge current and insulates the paired electrodes. A protective layer 105 is formed of oxide magnesium (MgO) on the dielectric layer 104 to facilitate a discharge condition.
The rear panel 110 includes stripe-type (or well-type) barrier ribs 112 for forming a plurality of discharge spaces or discharge cells arranged in parallel. The rear panel 110 includes a plurality of address electrodes 113 performing an address discharge are arranged in parallel with the barrier ribs 112. Red (R), green (G) and blue (B) phosphors 114 emit visible rays for displaying the image in the sustain discharge and are coated over an upper surface of the rear panel 110. A dielectric layer 115 for protecting the address electrode 113 is formed between the address electrode 113 and the phosphor 114.
FIG. 2a illustrates driving waveforms of a plasma display panel in a related art.
As shown in FIG. 2a, the plasma display panel is driven with a frame divided into a reset period for initializing the entire cells, an address period for selecting a cell to be discharged, a sustain period for sustaining the discharge of the selected cell and an erase period for erasing wall charges within discharged cells.
In the setup period of the reset period, a ramp-up waveform (Ramp-up) is applied to the entire scan electrodes at the same time. The ramp-up waveform generates a weak dark discharge within discharge cells of the entire screen. The setup discharge causes positive wall charges to be accumulated on the address electrodes and the sustain electrodes, negative wall charges to be accumulated on the scan electrodes.
In the setdown period of the reset period, after the ramp-up waveform is applied, a ramp-down waveform (Ramp-down), which starts falling from a positive voltage lower than a peak voltage of the ramp-up waveform up to a predetermined voltage level lower than a ground (GND) level voltage, generates a weak erase discharge within cells, thereby sufficiently erasing wall charges excessively formed on the scan electrodes. Wall charges sufficient for a stable address discharge are uniformly remained within the cells due to the the setdown discharge.
In the address period, while negative scan pulses are sequentially applied to the scan electrodes, address pulses having a positive polarity is applied to the address electrodes in synchronization with the scan pulse. As a voltage difference between the scan pulse and the address pulse and a wall voltage generated in the reset period are added, an address discharge is generated within discharge cells to which the address pulse is applied. Wall charges that can cause a discharge when a sustain voltage (Vs) is applied are generated within cells selected by an address discharge. The sustain electrodes are supplied with a positive voltage (Vz) in order that an erroneous discharge is not generated between the sustain electrode and the scan electrode by reducing the voltage difference between the sustain electrode and the scan electrode during the setdown period and the address period.
In the sustain period, a sustain pulse is alternately applied to the scan electrodes and the sustain electrodes. In a cell selected by an address discharge, a sustain discharge, i.e., a display discharge is generated between the scan electrodes and the sustain electrodes whenever the sustain pulse is applied as the wall voltage within the cell and the sustain pulse are added.
After the sustain discharge is completed, in the erase period, an erase ramp waveform (Ramp-ers) having a narrow pulse width and a low voltage level is applied to the sustain electrodes, thereby wall charges remaining within the cells of the entire screen are erased.
The distribution of wall charges in the discharge cell due to a driving pulse is shown in FIG. 2.
FIG. 2b illustrates wall charges distributed in a discharge cell according to driving pulses of a related art.
Referring to FIG. 2b, during the setup period, negative wall charges are formed in the scan electrode(Y), positive wall charges are formed in the sustain electrode(Z). During the setdown period, Ramp-Down waveform, falling from a positive voltage lower than the peak voltage of Ramp-Up waveform, is applied to the scan electrode. Accordingly, excessive wall charges which are unnecessary and unbalanced are erased, therefore, wall charges within a cell are decreased in a moderate amount.
Then, during the address period, a negative voltage is applied to the scan electrode(Y), a positive voltage is applied to the sustain electrode(Z). In this time, an address discharge is happened by adding the voltage, negative, of wall charges formed in a setdown period to the negative voltage applied to the scan electrode(Y).
The plasma display panel of the related art described above is able to generate a stable address discharge, only when optimized wall charges are formed during the reset period. However, sometimes, one can not obtain optimized wall charges according to the characteristics of the panel, which results in an error discharge and or an error writing of discharge cell.
FIG. 3 illustrates wall charges formed in some discharge cells among discharge cells according to driving pulses of a related art. As shown in FIG. 3, in some discharge cells, negative wall charges are formed in the scan electrode(Y), excessive positive wall charges are formed in an address electrode(X), in set down period. As described above, the positive wall charges excessively formed in the address electrode(X) undesirably performs an address discharge within the discharge cell to which data pulse is not applied. Therefore, a luminescent spot error discharge or a mistaken writing are happened to deteriorate the definition of a plasma display panel.